This invention relates to a power voltage drop detecting circuit and, more particularly, to a power voltage drop detecting circuit formed on, for example, a CMOS type microcomputer LSI chip.
Lately, microcomputer LSIs are used for controlling fuel injection in automobile engines. Most of these LSIs each contain a RAM for storing the important data generated for fuel injection control. Even when the CPU of the microcomputer is in the standby mode and not operating, the RAM must retain this data. However, when the power voltage supplied to the microcomputer LSI drops, there is a risk that the control data contains incorrect values. To avoid this risk, a voltage drop detecting circuit, which can detect a power voltage drop below a predetermined value, is provided in the LSI chip.
When the detection circuit detects a voltage drop, the data is prepared again and stored in the RAM. When no voltage drop is detected, the data is considered to have been correctly stored in the RAM. The data can be used for engine control after the CPU is released from the standby mode.
FIG. 1 shows a conventional power voltage drop detection circuit. This detecting circuit uses a pair of enhancement type MOS transistors Q1 and Q3 and another pair of depletion type MOS transistors Q2 and Q4. Transistors Q1 and Q2 form voltage dividing circuit 10 between VDD terminal and the ground terminal, while transistors Q3 and Q4 form inverter 12 for digitizing the output signal of the voltage dividing circuit 10. In operation, the output signal of voltage dividing circuit 10 lessens with the drop of the power voltage. When the power voltage falls below a predetermined value, the transistors of inverter 12 are turned off, and the inverter outputs a signal at a high level. The output signal is inverted by second inverter 14 and supplied to the reset terminal R of RS flip-flop 16. Flip-flop 16, in response to this signal, produces a high level signal from Q output terminal in the form of a power voltage detecting signal.
When the microcomputer LSI has a CMOS structure, the conventional power voltage drop detecting circuit has the following disadvantages. Only enhancement type MOS transistors are used, as circuit elements, for constructing CPU, RAMs, etc. For this reason, if depletion type MOS transistors of the detector circuit are to be formed together with enhancement type MOS transistors in the same semiconductor substrate, the manufacturing process is more complicated. As a result, the conventional detector circuit is expensive and cannot be readily used in microprocessor CMOS LSIs.
If the detector circuit of FIG. 1 comprises CMOS type elements, it could be arranged as shown in FIG. 2. This circuit uses n-channel type enhancement MOS transistor Q5 and diffusion resistor R for a voltage dividing circuit, and p-channel and n-channel type enhancement transistors Q6 and Q7 for a CMOS inverter. The output signal of the CMOS inverter is supplied to the reset terminal of CMOS flip-flop 18. Power source terminal VDD is connected to the input terminal of the voltage dividing circuit, that is to say, the gate of MOS transistor Q5.
In the detector circuit of FIG. 2, the current of in the order of at least 10.sup.-6 ampere flows at about room temperature. In the case of CMOS LSI, in the standby mode, the current in the order of 10.sup.-10 to 10.sup.-9 will flow in the same temperature condition. This current is generally used in inspecting for defective CMOS LSIs. When the standby current falls out of the specified range, the corresponding CMOS microcomputer LSI is considered defective.
The incorporating of the detector circuit of FIG. 2 into the CMOS LSI is undesirable in view of other factors than the manufacturing cost. The current consumed by this detector circuit is considerably larger than the standby current. The difference in standby current cannot be detected due to the fluctuation of the consumed current, so that it is difficult to use it for defective CMOS LSI testing.
FIG. 3 represents the relationship of the CMOS LSI standby current and the consumed current of the power supply voltage drop detector. The broken line shows the consumed current level of the power voltage drop detector circuit. Solid line A shows a relationship of the standby current of a correctly operating CMOS LSI to the ambient temperature. Solid line B shows the same relationship observed with a defective CMOS LSI. As FIG. 3 shows, the difference between the standby currents of good and defective MOS LSIs at room temperature can be clearly seen. Actually, however, the current consumed by the power voltage drop circuit shown in FIG. 2 eliminates these current differences.
For this reason, the power voltage drop detecting circuit of FIG. 2 cannot hardly be readily used in the CMOS LSI.